/specs

Specifications and sources

Every figure below was read from its source on 2026-10-15. A figure is stated by the vendor or a paper, derived from stated figures (the formula is in the model), reported by a third party, illustrative (a model parameter, labelled), or not disclosed in the sources used: gaps are never filled with a guess. Hover a source tag for the source's title, its access date and where in it the figure is. Availability: product (shipping or generally available), announced (announced, shipping not yet stated or only starting), retired (superseded or discontinued), research (a research chip, not a product). Bandwidths are per direction unless marked “both directions”; peak rates are dense unless marked sparse. The same tables, generated by the model's script, are in results.md.

The families

Family	Weights live in	Who schedules	Grain
GPUsNVIDIA H100, B200	off-chip DRAM[hopper-blog]	hardware, at run time[hopper-blog]	tens to hundreds of cores[hopper-blog]
Systolic designsGoogle TPU, AWS Trainium	off-chip DRAM[tpu-7x]	compiler, ahead of time[tpu-arch]	a few large engines[tpu-arch]
Wafer-scaleCerebras WSE-3	on-chip SRAM[cerebras-inference]	mixed[cerebras-wp]	hundreds of thousands of cores[cerebras-wp]
Compiler-scheduledGroq LPU	on-chip SRAM[groqchip-brief]	compiler, ahead of time[groq-isca22]	a few large engines[groq-isca22]
Reconfigurable dataflowSambaNova RDU, Graphcore IPU	tiered SRAM + DRAM[sn40l]	compiler, ahead of time[sn40l]	tens to hundreds of cores[ipu-dissect]
Meshes of small coresTenstorrent Blackhole	tiered SRAM + DRAM[tt-hardware]	mixed[tt-hardware]	tens to hundreds of cores[tt-hardware]
FPGAs and edge NPUsAMD Versal AI Engines, Apple Neural Engine	tiered SRAM + DRAM[amd-aie]	compiler, ahead of time[amd-aie]	tens to hundreds of cores[amd-aie]
In-memory and analoguephase-change crossbars (research)	in the memory array[pcm-imc]	compiler, ahead of time[pcm-imc]	tens to hundreds of cores[pcm-imc]

Parts

NVIDIA H100 SXM

Family: GPUs. Availability: product[h100-page]

	NVIDIA H100 SXM
BF16, dense	990 TFLOP/s (derived)[h100-page]
FP8, dense	1.98 PFLOP/s (derived)[h100-page]
INT8, dense	1.98 POP/s (derived)[h100-page]
On-chip SRAM	50 MB[hopper-blog]
SRAM bandwidth	not disclosed[hopper-blog]
Off-chip memory	80 GB[h100-page]
Off-chip bandwidth	3.35 TB/s[h100-page]
Chip-to-chip (both directions)	900 GB/s[h100-page]
Chip-to-chip hop latency	not disclosed[h100-page]
Power	700 W[h100-page]
Cores / SMs / TensorCores	132[hopper-blog]

NVIDIA B200 (as in GB200 NVL72)

Family: GPUs. Availability: product[gb200-page]

	NVIDIA B200 (as in GB200 NVL72)
BF16, dense	2.5 PFLOP/s (derived)[gb200-page]
FP8, dense	5 PFLOP/s[bwu-blog]
INT8, dense	5 POP/s (derived)[gb200-page]
FP4 (NVFP4 or MXFP4), dense	10 PFLOP/s[bwu-blog]
On-chip SRAM	not disclosed[bwu-blog]
SRAM bandwidth	not disclosed[bwu-blog]
Off-chip memory	186 GB (derived)[gb200-page]
Off-chip bandwidth	8 TB/s (derived)[gb200-page]
Chip-to-chip (both directions)	1.8 TB/s (derived)[gb200-page]
Chip-to-chip hop latency	not disclosed[gb200-page]
Power	1.2 kW[bwu-blog]
Cores / SMs / TensorCores	not disclosed[bwu-blog]

AMD Instinct MI355X

Family: GPUs. Availability: product[amd-mi355x]

	AMD Instinct MI355X
BF16, dense	2.5 PFLOP/s[amd-mi355x]
FP8, dense	5 PFLOP/s[amd-mi355x]
INT8, dense	5 POP/s[amd-mi355x]
FP4 (NVFP4 or MXFP4), dense	10.1 PFLOP/s[amd-mi355x]
On-chip SRAM	256 MB[amd-mi355x]
SRAM bandwidth	not disclosed[amd-mi355x]
Off-chip memory	288 GB[amd-mi355x]
Off-chip bandwidth	8 TB/s[amd-mi355x]
Chip-to-chip (both directions)	not disclosed[amd-mi355x]
Chip-to-chip hop latency	not disclosed[amd-mi355x]
Power	1.4 kW[amd-mi355x]
Cores / SMs / TensorCores	256[amd-mi355x]

Google TPU v6e (Trillium)

Family: Systolic designs. Availability: product[tpu-v6e]

	Google TPU v6e (Trillium)
BF16, dense	918 TFLOP/s[tpu-v6e]
FP8, dense	918 TFLOP/s[tpu-7x]
INT8, dense	1.84 POP/s[tpu-v6e]
On-chip SRAM	not disclosed[tpu-v6e]
SRAM bandwidth	not disclosed[tpu-v6e]
Off-chip memory	32 GB[tpu-v6e]
Off-chip bandwidth	1.638 TB/s[tpu-v6e]
Chip-to-chip (both directions)	800 GB/s[tpu-v6e]
Chip-to-chip hop latency	not disclosed[tpu-v6e]
Power	not disclosed[tpu-v6e]
Cores / SMs / TensorCores	2[tpu-v6e]
Systolic array rows	256[tpu-arch]
Systolic array columns	256[tpu-arch]

Google TPU7x (Ironwood)

Family: Systolic designs. Availability: product[tpu-7x]

	Google TPU7x (Ironwood)
BF16, dense	2.31 PFLOP/s[tpu-7x]
FP8, dense	4.61 PFLOP/s[tpu-7x]
INT8, dense	not disclosed[tpu-7x]
On-chip SRAM	not disclosed[tpu-7x]
SRAM bandwidth	not disclosed[tpu-7x]
Off-chip memory	192 GiB[tpu-7x]
Off-chip bandwidth	7.38 TB/s[tpu-7x]
Chip-to-chip (both directions)	1.2 TB/s[tpu-7x]
Chip-to-chip hop latency	not disclosed[tpu-7x]
Power	not disclosed[tpu-7x]
Cores / SMs / TensorCores	2[tpu-7x]
Systolic array rows	256[tpu-arch]
Systolic array columns	256[tpu-arch]

AWS Trainium2

Family: Systolic designs. Availability: product[trn2-arch]

	AWS Trainium2
BF16, dense	667 TFLOP/s[trn2-arch]
FP8, dense	1.3 PFLOP/s[trn2-arch]
INT8, dense	not disclosed[trn2-arch]
On-chip SRAM	224 MB (derived)[nc3-arch]
SRAM bandwidth	not disclosed[nc3-arch]
Off-chip memory	96 GiB[trn2-arch]
Off-chip bandwidth	2.9 TB/s[trn2-arch]
Chip-to-chip (both directions)	1.28 TB/s[trn2-arch]
Chip-to-chip hop latency	not disclosed[trn2-arch]
Power	not disclosed[trn2-arch]
Cores / SMs / TensorCores	8[trn2-arch]
Systolic array rows	128[nki-trn2]
Systolic array columns	128[nki-trn2]

Cerebras WSE-3 (CS-3)

Family: Wafer-scale. Availability: product[cs3-datasheet]

	Cerebras WSE-3 (CS-3)
FP16, sparse (vendor figure)	125 PFLOP/s[cs3-datasheet]
BF16, dense	not disclosed[cerebras-wp]
FP8, dense	not disclosed[cs3-datasheet]
INT8, dense	not disclosed[cs3-datasheet]
On-chip SRAM	44 GB[cs3-datasheet]
SRAM bandwidth	21 PB/s[cs3-datasheet]
Off-chip memory	none[cerebras-wp]
Off-chip bandwidth	none[cerebras-wp]
System I/O	1.2 Tb/s[cs3-datasheet]
Chip-to-chip (both directions)	not disclosed[cs3-datasheet]
Chip-to-chip hop latency	not disclosed[cs4-page]
Power	27 kW[cs3-datasheet]
Cores / SMs / TensorCores	900,000[cs3-datasheet]
Silicon area	46,225 mm²[cs3-datasheet]
Transistors	4 trillion[cs3-datasheet]
Defect tolerance	spare cores and routes; defects shut down and routed round[cerebras-chip]
Dies on the wafer	84[cerebras-wp]
Area per core	38,000 µm²[cerebras-wp]
SRAM per core	48 kB[cerebras-wp]
On-wafer fabric	214 Pb/s[cs3-datasheet]

Cerebras WSE-3 Turbo (CS-4) (announced)

Family: Wafer-scale. Availability: announced[cs4-page]

	Cerebras WSE-3 Turbo (CS-4)(announced)
FP16, sparse (vendor figure)	250 PFLOP/s[cs4-datasheet]
BF16, dense	not disclosed[cs4-datasheet]
FP8, dense	not disclosed[cs4-datasheet]
INT8, dense	not disclosed[cs4-datasheet]
On-chip SRAM	44 GB[cs4-datasheet]
SRAM bandwidth	43.2 PB/s[cs4-datasheet]
Off-chip memory	none[cs4-datasheet]
Off-chip bandwidth	none[cs4-datasheet]
System I/O	2.4 Tb/s[cs4-datasheet]
Chip-to-chip (both directions)	not disclosed[cs4-datasheet]
Chip-to-chip hop latency	2 µs[cs4-datasheet]
Power	not disclosed[cs4-datasheet]
Cores / SMs / TensorCores	900,000[cs4-datasheet]
Silicon area	46,225 mm²[cs4-datasheet]
Dies on the wafer	84[cerebras-wp]
Area per core	38,000 µm²[cerebras-wp]
SRAM per core	48 kB[cerebras-wp]
On-wafer fabric	428 Pb/s (derived)[cs4-datasheet]

GroqChip (first-generation LPU) (retired)

Family: Compiler-scheduled. Availability: retired[groqchip-brief]

	GroqChip (first-generation LPU)(retired)
BF16, dense	not disclosed[groqchip-brief]
FP16, dense	188 TFLOP/s[groqchip-brief]
FP8, dense	not disclosed[groqchip-brief]
INT8, dense	750 TOP/s[groqchip-brief]
On-chip SRAM	230 MB[groqchip-brief]
SRAM bandwidth	80 TB/s[groqchip-brief]
Off-chip memory	none[groqchip-brief]
Off-chip bandwidth	none[groqchip-brief]
Chip-to-chip links	16[groqchip-brief]
One link, per direction	100 Gb/s[groq-isca22]
Chip-to-chip (both directions)	400 GB/s (derived)[groq-isca22]
Chip-to-chip hop latency	722 ns[groq-isca22]
Chips per node	8[groq-isca22]
Power	215 W[groqchip-brief]
Clock	900 MHz[groqchip-brief]
Process	14 nm[groqchip-brief]

NVIDIA Groq 3 LPU (LPX rack) (announced)

Family: Compiler-scheduled. Availability: announced[groq-home]

	NVIDIA Groq 3 LPU (LPX rack)(announced)
BF16, dense	not disclosed[lpx-page]
FP8, dense	1.23 PFLOP/s (derived)[groq-home]
INT8, dense	not disclosed[lpx-page]
On-chip SRAM	500 MB[lpx-page]
SRAM bandwidth	150 TB/s[lpx-page]
Off-chip memory	none[lpx-page]
Off-chip bandwidth	none[lpx-page]
Chip-to-chip (both directions)	2.5 TB/s[lpx-page]
Chip-to-chip hop latency	not disclosed[lpx-page]
Power	not disclosed[lpx-page]
Chips per rack	256[lpx-page]

SambaNova SN40L RDU

Family: Reconfigurable dataflow. Availability: product[sambanova-rdu]

	SambaNova SN40L RDU
BF16, dense	638 TFLOP/s[sn40l]
FP8, dense	not disclosed[sn40l]
INT8, dense	not disclosed[sn40l]
On-chip SRAM	520 MB[sn40l]
SRAM bandwidth	not disclosed[sn40l]
Off-chip memory	64 GB[sn40l]
Off-chip bandwidth	1.8 TB/s[sn40l]
DDR (third tier)	1.5 TB[sn40l]
DDR bandwidth	200 GB/s[sn40l]
Chip-to-chip (both directions)	not disclosed[sn40l]
Chip-to-chip hop latency	not disclosed[sn40l]
Power	not disclosed[sambanova-rdu]
Cores / SMs / TensorCores	1,040[sn40l]
Process	5 nm[sn40l]

Graphcore GC2 IPU (first generation) (retired)

Family: Reconfigurable dataflow. Availability: retired[graphcore-home]

	Graphcore GC2 IPU (first generation)(retired)
BF16, dense	not disclosed[ipu-dissect]
FP16, dense	125 TFLOP/s[ipu-dissect]
FP8, dense	not disclosed[ipu-dissect]
INT8, dense	not disclosed[ipu-dissect]
On-chip SRAM	319 MB[ipu-dissect]
SRAM bandwidth	45 TB/s[ipu-dissect]
Off-chip memory	none[ipu-dissect]
Off-chip bandwidth	none[ipu-dissect]
Chip-to-chip (both directions)	not disclosed[ipu-dissect]
Chip-to-chip hop latency	not disclosed[ipu-dissect]
Power	150 W (reported)[ipu-dissect]
Cores / SMs / TensorCores	1,216[ipu-dissect]
SRAM per tile	262 kB[ipu-dissect]

Tenstorrent Blackhole (p150a card)

Family: Meshes of small cores. Availability: product[tt-hardware]

	Tenstorrent Blackhole (p150a card)
BF16, dense	not disclosed[tt-hardware]
FP8, dense	664 TFLOP/s[tt-hardware]
INT8, dense	not disclosed[tt-hardware]
On-chip SRAM	180 MB[tt-hardware]
SRAM bandwidth	not disclosed[tt-hardware]
Off-chip memory	32 GB[tt-hardware]
Off-chip bandwidth	512 GB/s[tt-hardware]
Chip-to-chip (both directions)	800 GB/s (derived)[tt-hardware]
Chip-to-chip hop latency	not disclosed[tt-hardware]
Power	300 W[tt-hardware]
Cores / SMs / TensorCores	120[tt-hardware]
'Big RISC-V' cores	16[tt-hardware]
Clock	1,350 MHz[tt-hardware]

Apple M4 (Neural Engine)

Family: FPGAs and edge NPUs. Availability: product[apple-mbp-m4]

	Apple M4 (Neural Engine)
BF16, dense	not disclosed[apple-m4]
FP8, dense	not disclosed[apple-m4]
INT8, dense	38 TOP/s[apple-m4]
On-chip SRAM	not disclosed[apple-m4]
SRAM bandwidth	not disclosed[apple-m4]
Off-chip memory	32 GB[apple-mbp-m4]
Off-chip bandwidth	120 GB/s[apple-mbp-m4]
Chip-to-chip (both directions)	not disclosed[apple-m4]
Chip-to-chip hop latency	not disclosed[apple-m4]
Power	not disclosed[apple-m4]
Cores / SMs / TensorCores	16[apple-m4]

Parts quoted, not modelled

Each lacks a figure the model needs (a memory capacity or bandwidth), so the chapters quote them and run nothing on them:

SambaNova SN50 RDU (announced)

Family: Reconfigurable dataflow. Availability: announced[sambanova-rdu]

	SambaNova SN50 RDU(announced)
BF16, dense	1.6 PFLOP/s[sambanova-rdu]
FP8, dense	3.2 PFLOP/s[sambanova-rdu]
On-chip SRAM	432 MB[sambanova-rdu]
Off-chip memory	64 GB[sambanova-rdu]
Off-chip bandwidth	not disclosed[sambanova-rdu]
DDR (third tier)	512 GB[sambanova-rdu]
Scale-up, chips	256[sambanova-rdu]

AMD Alveo V70 (Versal AI Core) (retired)

Family: FPGAs and edge NPUs. Availability: retired[amd-v70-part]

	AMD Alveo V70 (Versal AI Core)(retired)
INT8, dense	404 TOP/s[amd-v70]
BF16, dense	202 TFLOP/s[amd-v70]
SRAM bandwidth	47.6 TB/s[amd-v70]
Off-chip memory	not disclosed[amd-v70]
Off-chip bandwidth	76.8 GB/s[amd-v70]
Power	75 W[amd-v70]

AMD Alveo V80 (Versal HBM)

Family: FPGAs and edge NPUs. Availability: product[amd-v80]

	AMD Alveo V80 (Versal HBM)
INT8, dense	not disclosed[amd-v80]
BF16, dense	not disclosed[amd-v80]
On-chip SRAM	84.1 MB (derived)[amd-v80]
Off-chip memory	32 GB[amd-v80]
Off-chip bandwidth	820 GB/s[amd-v80]
Look-up tables	2,600,000[amd-v80]
DSP slices	10,848[amd-v80]
Power	190 W[amd-v80]

Hailo-10H (M.2 module)

Family: FPGAs and edge NPUs. Availability: product[hailo-10h]

	Hailo-10H (M.2 module)
INT4, dense	40 TOP/s[hailo-10h]
INT8, dense	20 TOP/s[hailo-10h]
Off-chip memory	8 GB[hailo-10h]
Off-chip bandwidth	not disclosed[hailo-10h]
Power	2.5 W[hailo-10h]

In-memory compute (chapter 9)

IBM HERMES project chip (PCM, research) (research)

Availability: research[pcm-imc]

	IBM HERMES project chip (PCM, research)(research)
Crossbar cores	64[pcm-imc]
Crossbar rows	256[pcm-imc]
Crossbar columns	256[pcm-imc]
Weights on chip	4,194,304[pcm-imc]
PCM devices per weight	4[pcm-imc]
MVM latency, 1-phase	133 ns[pcm-imc]
MVM latency, 4-phase	520 ns[pcm-imc]
Energy, 64 MVMs, 1-phase	0.86 µJ[pcm-imc]
Energy, 64 MVMs, 4-phase	3.38 µJ[pcm-imc]
Peak MVM rate, 1-phase	63.1 TOP/s[pcm-imc]
Peak MVM rate, 4-phase	16.1 TOP/s[pcm-imc]
Efficiency, 1-phase	9.76 TOPS/W[pcm-imc]
Efficiency, 4-phase	2.48 TOPS/W[pcm-imc]
Input/output bits	8[pcm-imc]
Die area	144 mm² (derived)[pcm-imc]
Process	14 nm[pcm-imc]

Published figures (checks, not inputs)

MLPerf v4.0, 8x H100, Llama 2 70B, Offline (tokens/s)	21,800[mlperf-h100]
MLPerf Llama 2 70B, output tokens per sample	294[mlperf-llama2]
mlperf-input-mean	222 (derived)[mlperf-dataset]
mlperf-gb200	51,700[mlperf-gb200]
mlperf-gb200-chips	4[mlperf-gb200]
Cerebras: CS-3 systems for a 70B model	4[cerebras-inference]
Cerebras: CS-3 systems for a 20B model	1[cerebras-inference]
Cerebras: Llama 3.1 8B (tokens/s)	1,800[cerebras-inference]
Cerebras: Llama 3.1 70B (tokens/s)	450[cerebras-inference]
Groq demonstration: GroqChips for Llama 2 70B	576 (reported)[nextplatform-groq]
Groq demonstration: Llama 2 70B (tokens/s per user)	300 (reported)[nextplatform-groq]
sn40l-sockets	16[sn40l]
sn40l-8b-tps	1,040[sn40l]
sn40l-70b-tps	457[sn40l]

Illustrative parameters

Chosen for chapter 4's picture, not measured or published:

Defect density (per cm²)	0.1 (illustrative)[cerebras-wp]
Reticle-sized die for comparison (mm²)	814 (illustrative)[hopper-blog]
Share of cores held as spares	0.015 (illustrative)[cerebras-wp]

Quoted claims

Shown where relevant, attributed, and never used as model inputs:

CS-4 'delivers up to 30x faster inference compared to GPU systems' (Cerebras CS-4 system page ('First CS-4 shipments begin this quarter'))
CS-4 'delivers more than 1,000 tokens per second on models exceeding 50 trillion parameters' (the page; the datasheet says 10 trillion) (Cerebras CS-4 system page ('First CS-4 shipments begin this quarter'))
Cerebras Inference 'runs Llama3.1 20x faster than GPU solutions at 1/3 the power of DGX solutions' (Cerebras blog, 'Introducing Cerebras Inference: AI at Instant Speed' (August 2024))
an LPX rack: '1,000 tokens/sec/user' (Groq home page, LPX rack figures ('When released, each NVIDIA Groq 3 LPX rack connects 256 next-generation LPU accelerators'))
Cerebras cores reach 'as high as 10x more utilization than GPUs on unstructured, sparse compute' (Cerebras white paper, 'The Cerebras Wafer-Scale Architecture for Deep Learning' (PDF))
SN40L: 'Dataflow enables overlapping weight loads with computation to achieve over 85% of HBM bandwidth' (the SN40L paper; it says GPU implementations 'rarely exceed 50%') (Prabhakar et al., 'SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts', arXiv:2405.07518)
FlightLLM on an Alveo U280: '6.0x higher energy efficiency and 1.8x better cost efficiency against commercial GPUs (e.g., NVIDIA V100S) on modern LLMs (e.g., LLaMA2-7B)' at batch 1; on a Versal VHK158, '1.2x higher throughput' than an A100 (Zeng et al., 'FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs', FPGA 2024, arXiv:2401.03868)
a spatial (one unit per operator) GPT-2 design on an Alveo U280: 'a 1.9x speedup and a 5.7x improvement in energy efficiency compared to the NVIDIA A100 GPU in the decode stage', with a library of HLS kernels (Chen et al., 'Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference', arXiv:2312.15159)
FINN builds FPGA accelerators for binarized networks as 'a flexible heterogeneous streaming architecture', 'with per-layer compute resources being tailored to user-provided throughput requirements': up to 12.3 million MNIST classifications per second at 0.31 us latency, under 25 W (Umuroglu et al., 'FINN: A Framework for Fast, Scalable Binarized Neural Network Inference', FPGA 2017, arXiv:1612.07119)
hls4ml, 'a package based on High-Level Synthesis', builds neural networks into FPGAs for particle-physics triggers; the example jet classifier fits 'with a latency on the scale of 100 ns' (Duarte et al., 'Fast inference of deep neural networks in FPGAs for particle physics' (hls4ml), JINST 2018, arXiv:1804.06913)
M4's Neural Engine is 'faster than the neural processing unit of any AI PC today' (Apple, May 2024) (Apple Newsroom, 'Apple introduces M4 chip' (2024-05-07; Neural Engine 38 trillion operations per second))

Sources

h100-page: NVIDIA H100 product page, Product Specifications (H100 SXM column) (vendor product page, read 2026-10-15)
hopper-blog: NVIDIA Hopper Architecture In-Depth (NVIDIA Technical Blog) (vendor technical blog, read 2026-10-15)
gb200-page: NVIDIA GB200 NVL72 product page, Specifications, GB200 Superchip column ('Specification in sparse. Dense is one-half sparse spec shown') (vendor product page, read 2026-10-15)
bwu-blog: Inside NVIDIA Blackwell Ultra: The Chip Powering the AI Factory Era (NVIDIA Technical Blog), Table 2 (vendor technical blog, read 2026-10-15)
hgx-page: NVIDIA HGX platform page, HGX B200 specifications ('Specification in Sparse. Dense is 1/2 sparse spec shown') (vendor product page, read 2026-10-15)
tpu-arch: Google Cloud TPU documentation: TPU architecture (TensorCores and MXUs) (vendor documentation, read 2026-10-15)
tpu-v6e: Google Cloud TPU documentation: TPU v6e (Trillium), system architecture table (vendor documentation, read 2026-10-15)
tpu-7x: Google Cloud TPU documentation: TPU7x (Ironwood), system architecture table and memory hierarchy (vendor documentation, read 2026-10-15)
trn2-arch: AWS Neuron documentation: Trainium2 architecture (vendor documentation, read 2026-10-15)
nc3-arch: AWS Neuron documentation: NeuronCore-v3 architecture (on-chip SRAM, Tensor Engine) (vendor documentation, read 2026-10-15)
nki-trn2: AWS Neuron documentation: NKI, Trainium2 architecture guide (TensorE PE grid) (vendor documentation, read 2026-10-15)
cs3-datasheet: Cerebras, 'The World's Fastest AI Infrastructure': CS-3 and WSE-3 datasheet (PDF; 'FLOPS shown as sparse') (vendor datasheet, read 2026-10-15)
cerebras-wp: Cerebras white paper, 'The Cerebras Wafer-Scale Architecture for Deep Learning' (PDF) (vendor white paper, read 2026-10-15)
cs4-datasheet: Cerebras, 'Meet CS-4' datasheet (PDF; 'AI compute shown as sparse FP16') (vendor datasheet, read 2026-10-15)
cs4-page: Cerebras CS-4 system page ('First CS-4 shipments begin this quarter') (vendor product page, read 2026-10-15)
cerebras-chip: Cerebras WSE-3 Turbo chip page ('How Cerebras Solved the Yield Problem') (vendor product page, read 2026-10-15)
cerebras-inference: Cerebras blog, 'Introducing Cerebras Inference: AI at Instant Speed' (August 2024) (vendor blog, read 2026-10-15)
groqchip-brief: Groq, GroqChip Processor Product Brief v1.5 (2022; Internet Archive copy of groq.com) (vendor datasheet, read 2026-10-15)
groq-isca22: Abts et al., 'A Software-defined Tensor Streaming Multiprocessor for Large-scale Machine Learning', ISCA 2022 (Groq's copy, Internet Archive) (paper (ISCA 2022), read 2026-10-15)
lpx-page: NVIDIA Groq 3 LPX product page (LPU accelerator and rack) (vendor product page, read 2026-10-15)
groq-home: Groq home page, LPX rack figures ('When released, each NVIDIA Groq 3 LPX rack connects 256 next-generation LPU accelerators') (vendor product page, read 2026-10-15)
nextplatform-groq: The Next Platform, 'Groq Says It Can Deploy 1 Million AI Inference Chips In Two Years' (2023-11-27): Groq's Llama 2 70B demonstration (trade press (reports a vendor demonstration), read 2026-10-15)
mlperf-h100: MLCommons, MLPerf Inference v4.0 results: NVIDIA DGX H100 (8x H100-SXM-80GB, TensorRT), llama2-70b-99.9, Offline, mlperf_log_summary.txt (benchmark result log, read 2026-10-15)
mlperf-llama2: MLCommons inference reference implementation, Llama 2 70B README ('Tokens per sample: 294.45') (benchmark documentation, read 2026-10-15)
nv-mlperf-v40: NVIDIA Technical Blog, 'NVIDIA H200 Tensor Core GPUs and NVIDIA TensorRT-LLM Set MLPerf LLM Inference Records' (MLPerf Inference v4.0; FP8 quantization) (vendor technical blog, read 2026-10-15)
llama3: Grattafiori et al., 'The Llama 3 Herd of Models', arXiv:2407.21783 (Table 3) (paper, read 2026-10-15)
llama2: Touvron et al., 'Llama 2: Open Foundation and Fine-Tuned Chat Models', arXiv:2307.09288 (paper, read 2026-10-15)
sze-survey: Sze, Chen, Yang and Emer, 'Efficient Processing of Deep Neural Networks: A Tutorial and Survey', arXiv:1703.09039 (paper, read 2026-10-15)
sn40l: Prabhakar et al., 'SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts', arXiv:2405.07518 (paper, read 2026-10-15)
sambanova-rdu: SambaNova, RDU chip page (SN50: dataflow execution, tiered memory) (vendor product page, read 2026-10-15)
ipu-dissect: Jia, Tillman, Maggioni and Scarpazza, 'Dissecting the Graphcore IPU Architecture via Microbenchmarking', arXiv:1912.03413 (paper, read 2026-10-15)
tt-hardware: Tenstorrent hardware page (Blackhole: Tensix cores, 'big RISC-V' cores, GDDR6, QSFP-DD 800G ports) (vendor product page, read 2026-10-15)
amd-aie: AMD AI Engine technology page (Versal adaptive SoCs: 2-D array of VLIW SIMD tiles with local memory) (vendor product page, read 2026-10-15)
apple-m4: Apple Newsroom, 'Apple introduces M4 chip' (2024-05-07; Neural Engine 38 trillion operations per second) (vendor press release, read 2026-10-15)
pcm-imc: Le Gallo et al., 'A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference', arXiv:2212.02872 (paper, read 2026-10-15)
sambanova-sn50-ds: SambaNova SN50 RDU datasheet (PDF; three-tier memory, 'DDR5 Up to 2 TB') (vendor datasheet, read 2026-10-15)
graphcore-home: Graphcore home page (lists no IPU products; graphcore.ai/products returns 404 on the access date) (vendor home page, read 2026-10-15)
apple-mbp-m4: Apple Newsroom, 'New MacBook Pro features M4 family of chips and Apple Intelligence' (2024-10-30; M4: up to 32GB unified memory, 120GB/s) (vendor press release, read 2026-10-15)
amd-v70: AMD Alveo V70 accelerator card page, Specifications (XDNA, Versal AI Core, AIE-ML tiles) (vendor product page, read 2026-10-15)
amd-v70-part: AMD Alveo V70 part page a-v70-p16g-pq-g ('Discontinued: This product has been discontinued and is no longer offered for sale') (vendor product page, read 2026-10-15)
hailo-10h: Hailo-10H M.2 AI acceleration module page (40|20 TOPS INT4|INT8, 2.5W typical, 4|8GB LPDDR4/4X) (vendor product page, read 2026-10-15)
amd-mi355x: AMD Instinct MI355X product page, Specifications (launch date 6/12/2025) (vendor product page, read 2026-10-16)
amd-v80: AMD Alveo V80 compute accelerator card, part page A-V80-P64G-PQ-G, General Specifications (Versal HBM XCV80; 'Buy') (vendor product page, read 2026-10-16)
mlperf-gb200: MLCommons, MLPerf Inference v5.1 results: NVIDIA GB200 NVL72 (4x GB200-186GB, one tray, TensorRT), llama2-70b-99.9, Offline, mlperf_log_summary.txt (weights FP4 per the submission's measurements JSON) (benchmark result log, read 2026-10-16)
mlperf-gb200-meas: MLCommons, MLPerf Inference v5.1: the same submission's measurements JSON ('weight_data_types': 'fp4') (benchmark submission metadata, read 2026-10-16)
mlperf-dataset: MLCommons, the MLPerf Llama 2 70B dataset (the 24,576-sample file and its MD5, as the bucket's manifest lists them): prompt lengths averaged by the site's scripts/mlperf_input_length.py (benchmark dataset, read 2026-10-16)
flightllm: Zeng et al., 'FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs', FPGA 2024, arXiv:2401.03868 (peer-reviewed paper, read 2026-10-16)
chen-spatial: Chen et al., 'Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference', arXiv:2312.15159 (paper, read 2026-10-16)
finn: Umuroglu et al., 'FINN: A Framework for Fast, Scalable Binarized Neural Network Inference', FPGA 2017, arXiv:1612.07119 (peer-reviewed paper, read 2026-10-16)
hls4ml: Duarte et al., 'Fast inference of deep neural networks in FPGAs for particle physics' (hls4ml), JINST 2018, arXiv:1804.06913 (peer-reviewed paper, read 2026-10-16)